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19-1013; Rev 0; 11/07
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability
General Description
The MAX16050 monitors up to 5 voltages and sequences up to 4 voltages, while the MAX16051 monitors up to 6 voltages and sequences up to 5 voltages. These devices provide an adjustable delay as each supply is turned on and they monitor each power-supply voltage. When all of the voltages reach their final values and the reset delay timer expires, a power-on-reset (POR) output deasserts allowing the microcontroller (C) to operate. If any voltage falls below its threshold, the reset output asserts and all voltage supplies are turned off. The MAX16050/MAX16051 can be daisy-chained to control a higher number of voltages in a system. During a power-down event, the MAX16050/MAX16051 can reverse sequence the outputs. In this situation, each voltage is turned off sequentially until it reaches a 250mV level, at which point, the next supply is turned off. The MAX16050/MAX16051 also provide internal pulldown circuitry that turns on during power-down, to help discharge large output capacitors. The MAX16050/MAX16051 feature a charge-pump supply output that can be used as a pullup voltage for driving external n-channel MOSFETs and an overvoltage output that indicates when any of the monitored voltages exceeds its overvoltage threshold. The MAX16050 also provides three sequence control inputs for changing the sequence order, while the MAX16051 has a fixed sequence order. The MAX16050/MAX16051 are available in a 28-pin (4mm x 4mm) thin QFN package and are fully specified over the -40C to +85C extended operating temperature range.
Features
Monitor Up to 6 Voltages/Sequence Up to 5 Voltages Pin-Selectable Sequencing Order (MAX16050 Only) Reverse-Sequencing Capability on Shutdown Overvoltage Monitoring with Independent Output 1.5% Threshold Accuracy 2.7V to 13.2V Operating Voltage Range Charge Pump to Fully Enhance External n-Channel FETs Capacitor-Adjustable Sequencing Delay Fixed or Capacitor-Adjustable Reset Timeout Internal 85mA Pulldowns for Discharging Capacitive Loads Quickly Daisy-Chaining Capability to Communicate Across Multiple Devices Small 4mm x 4mm, 28-Pin TQFN Package
MAX16050/MAX16051
Pin Configurations
FAULT RESET OV_OUT OUT1 SET1 REM 15 14 13 12 EN_HOLD DISC2 OUT2 SET2 DISC3 OUT3 SET3 11 10 9 8 1 VCC 2 GND 3 ABP 4 EN 5 SET4 6 OUT4 7 DISC4
TOP VIEW
21 SHDN 22 DELAY 23 TIMEOUT 24 SEQ1 25 SEQ2 26 SEQ3 27 CP_OUT 28
20
19
18
17
16
MAX16050
*EP
Applications
Servers Workstations Networking Systems
Typical Operating Circuit appears at end of data sheet.
+
Telecom Equipment Storage Systems
*EP = EXPOSED PAD
THIN QFN (4mm x 4mm)
Pin Configurations continued at end of data sheet.
Ordering Information
PART MAX16050ETI+ MAX16051ETI+ MONITORED VOLTAGES 5 6 VOLTAGES SEQUENCED 4 5 PIN-PACKAGE 28 TQFN-EP* 28 TQFN-EP* PACKAGE CODE T2844-1 T2844-1
Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes lead-free package. *EP = Exposed pad.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
DISC1
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) VCC .........................................................................-0.3V to +30V REM, OUT_, DISC_.................................................-0.3V to +30V RESET, SHDN, SET_, FAULT, EN_HOLD, EN, DELAY, OV_OUT, ABP, TIMEOUT, SEQ_...........................-0.3V to +6V CP_OUT.........................................................-0.3V to (VCC + 6V) RESET Current ....................................................................50mA DISC_ Current ...................................................................180mA Input/Output Current (all other pins) ...................................20mA Continuous Power Dissipation (TA = +70C) 28-Pin (4mm x 4mm) Thin QFN (derate 28.6mW/C above +70C) ............................................................2285mW* Operating Temperature Range ...........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C *As per JEDEC51 Standard (Multilayer Board).
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 13.2V, VEN = VABP, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Operating Voltage Range (Note 2) Operating Voltage Regulated Supply Voltage Undervoltage Lockout Undervoltage Lockout Hysteresis Supply Current MONITORED ANALOG INPUTS SET_ Threshold SET_ Threshold Hysteresis SET1-SET4 Input Current SET5 Input Current SET_ Threshold Tempco Overvoltage Threshold Overvoltage Threshold Hysteresis EN Threshold EN Threshold Hysteresis EN Input Current VTH_EN VEN_HYS IEN VTH VTH_HYS ISET ISET5 VTH/_TC VTH_OV SET_ falling SET_ rising EN_ falling EN_ rising VEN = 0.5V VCC = 3.3V, ISINK = 3.2mA VCC = 1.8V, ISINK = 100A VOUT_ = 12V, OUT_ asserted Pulldown current during fault condition or power-down mode, VDISC_ = 1V VDISC_ = 3.3V, not in power-down mode DISC_ falling 200 250 85 1 300 -100 0.492 0.541 SET_ falling SET_ rising VSET_ = 0.5V VSET5 = 0.5V (MAX16051 only) -100 -30 30 0.55 0.5 0.5 0.5 +100 0.3 0.3 1 0.508 0.558 0.492 0.5 0.5 +100 +30 0.508 V %VTH nA A ppm/C V %VTH_OV V %VTH_EN nA SYMBOL VCC VCCR VABP VUVLO ICC CONDITIONS Voltage on VCC to ensure the device is fully operational VDISC_ = VOUT_ = VRESET = low, voltage on VCC rising IABP = 1mA (external sourcing current from ABP) Minimum voltage on ABP, ABP rising VCC = 3.3V, all OUT_ = high, no load 2.45 2.1 2.3 100 0.7 1.1 MIN 2.7 1.8 2.90 TYP MAX 13.2 UNITS V V V V mV mA
VUVLO_HYS ABP falling
SEQUENCING, CAPACITOR DISCHARGE, AND SEQUENCE TIMING OUTPUTS OUT_ Output Low Voltage OUT_ Leakage Current DISC_ Output Pulldown Current DISC_ Output Leakage Current DISC_ Power Low Threshold VOL_OUT ILKG_OUT IOL_DISC ILKG_DISC VTH_PL V A mA A mV
2
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.7V to 13.2V, VEN = VABP, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DELAY, TIMEOUT Output Source Current DELAY, TIMEOUT Threshold Voltage DIGITAL INPUTS/OUTPUTS SHDN, FAULT, EN_HOLD InputLogic Low Voltage SHDN, FAULT, EN_HOLD InputLogic High Voltage EN_HOLD Input Current EN_HOLD to OUT Delay FAULT, SHDN to ABP Pullup Resistance SHDN to OUT_ Delay RESET Output Low Voltage REM, FAULT Output Low Voltage FAULT Pulse Width SET_ to FAULT Delay Time SEQ1-SEQ3 Logic-High Level SEQ1-SEQ3 Logic HighImpedance (No Connect) Level SEQ1-SEQ3 Logic-Low Level SEQ1-SEQ3 High-Impedance State Tolerance Current RESET CIRCUIT RESET, REM, OV_OUT Output Leakage RESET Timeout Period OUT_, FAULT, SHDN to RESET Delay CHARGE-PUMP OUTPUT CP_OUT Voltage CP_OUT Source Current VCP_OUT ICP_OUT ICP_OUT = 0.5A VCP_OUT = VCC + 2V VCC + 4.6 17 VCC + 5 25 VCC + 5.8 30 V A ILKG tRP tRST VRESET = VREM = VOV_OUT = 5V TIMEOUT = ABP TIMEOUT = unconnected 50 128 3 1 300 A ms s VIL VIH II tEN_OUT RP tOUT VOL VOL_RF tFAULT_PW tSET_FAULT SET_ falling below respective threshold VIH_SEQ VIX_SEQ VIL_SEQ IIX MAX16050 only MAX16050 only MAX16050 only MAX16050 (Note 3) -6 VABP 0.35 0.92 1.45 0.33 +6 VCC = 3.3V, ISINK = 3.2mA VCC = 1.8V, ISINK = 100A VCC = 3.3V, ISINK = 3.2mA 1.9 2.5 60 3 100 12 0.3 0.3 0.3 160 2 1 0.4 V V A s k s V V s s V V V A SYMBOL IDT VTH_DT CONDITIONS VDELAY = VTIMEOUT = 0V MIN 1.7 1.218 TYP 2.5 1.250 MAX 3.0 1.281 UNITS A V
MAX16050/MAX16051
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA = +25C and TA = +85C. Specifications at TA = -40C are guaranteed by design. Note 2: When the voltage is below the VUVLO and above VCCR, OUT_ and RESET are asserted low. Note 3: SEQ1-SEQ3 are inputs with three logic levels: high, low, and high-impedance. _______________________________________________________________________________________ 3
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
Typical Operating Characteristics
(VCC = 5V; VEN = VABP, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX16050/51 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX16050/51 toc02
NORMALIZED SET_ THRESHOLD VOLTAGE vs. TEMPERATURE
NORMALIZED SET_ THRESHOLD VOLTAGE 1.004 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 -40 -15 10 35 60 85 NORMALIZED AT TA = +25C VSET_ FALLING
MAX16050/51 toc03
750
750 VCC = 5V ALL OUT_ = HIGH NO LOAD
1.005
700 SUPPLY CURRENT (A)
700 SUPPLY CURRENT (A)
650
650
600 TA = +25C 550 TA = -40C
TA = +85C
600
550
500 2.7 4.2 5.7 7.2 8.7 10.2 11.7 13.2 SUPPLY VOLTAGE (V)
500 -40 -15 10 35 60 85 TEMPERATURE (C)
TEMPERATURE (C)
NORMALIZED SEQUENCE DELAY vs. TEMPERATURE
MAX16050/51 toc04
SEQUENCE DELAY vs. CDELAY
MAX16050/51 toc05
NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE
NORMALIZED RESET TIMEOUT PERIOD 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 TIMEOUT = ABP TIMEOUT = OPEN NORMALIZED AT TA = +25C
MAX16050/51 toc06
1.20 NORMALIZED AT TA = +25C NORMALIZED SEQUENCE DELAY 1.15 1.10 1.05 1.00 0.95 0.90 CDELAY = 0.1F 0.85 0.80 -40 -15 10 35 60 CDELAY = OPEN
250
1.10
200 SEQUENCE DELAY (ms)
150
100
50
0 85 0 100 200 300 400 500 TEMPERATURE (C) CDELAY (nF)
0.90 -40 -15 10 35 60 85 TEMPERATURE (C)
RESET TIMEOUT PERIOD vs. CTIMEOUT
MAX16050/51 toc07
CP_OUT VOLTAGE vs. CP_OUT CURRENT
10 9 CP_OUT VOLTAGE (V) 8 7 6 5 4 3 2 1 0
MAX16050/51 toc08
250
11
RESET TIMEOUT PERIOD (ms)
200
150
100
50
0 0 100 200 300 400 500 CTIMEOUT (nF)
0
5
10
15
20
25
CP_OUT CURRENT (A)
4
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
Typical Operating Characteristics (continued)
(VCC = 5V; VEN = VABP, TA = +25C, unless otherwise noted.)
OV_OUT LOW VOLTAGE vs. SINK CURRENT
MAX16050/51 toc09
OUT_ LOW VOLTAGE vs. SINK CURRENT
MAX16050/51 toc10
RESET LOW VOLTAGE vs. SINK CURRENT
0.7 RESET LOW VOLTAGE (V) 0.6 0.5 0.4 0.3 0.2 0.1 0
MAX16050/51 toc11
0.8 0.7 OV_OUT LOW VOLTAGE (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 4 8 12 16
0.8 0.7 OUT_ LOW VOLTAGE (V) 0.6 0.5 0.4 0.3 0.2 0.1 0
0.8
20
0
4
8
12
16
20
0
4
8
12
16
20
SINK CURRENT (mA)
SINK CURRENT (mA)
SINK CURRENT (mA)
REVERSE SEQUENCE POWER-DOWN USING SHDN (CDELAY = CTIMEOUT = OPEN)
MAX1650/51 toc12
SIMULTANEOUS POWER-DOWN USING EN (CDELAY = CTIMEOUT = OPEN)
MAX1650/51 toc13
SHDN 5V/div V1 5V/div V2 5V/div V3 5V/div V4 5V/div 40s/div 40s/div
EN 5V/div V1 5V/div V2 5V/div V3 5V/div V4 5V/div
DAISY-CHAINING TWO DEVICES WITH SHDN RISING (FIGURE 7)
MAX1650/51 toc14a
DAISY-CHAINING TWO DEVICES WITH SHDN FALLING (FIGURE 7)
MAX1650/51 toc14b
SHDN V1 V2 V3 V4 V5 V6 V7 100s/div CDELAY (U1) = CDELAY (U2) = 100pF SHDN = 5V/div V1-V7 = 5V/div 10s/div CDELAY (U1) = CDELAY (U2) = 100pF SHDN = 5V/div V1-V7 = 5V/div
SHDN V1 V2 V3 V4 V5 V6 V7
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5
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
Pin Description
PIN MAX16050 1 2 3 MAX16051 1 2 3 NAME VCC GND ABP FUNCTION Device Power-Supply Input. Connect to 2.7V to 13.2V. Bypass VCC to GND with a 0.1F capacitor. Ground Internal Supply Bypass Input. Connect a 1F capacitor from ABP to GND. ABP is an internally generated voltage and must not be used to supply more than 1mA to external circuitry. Analog Enable Input. Connect a resistive divider at EN to monitor a voltage. The EN threshold is 0.5V. Set Monitored Threshold 4 Input. Monitor a voltage by setting the threshold with an external resistive divider. The SET4 threshold is 0.5V. Open-Drain Output 4. When the voltage at SET3* is above 0.5V, OUT4 goes high impedance. OUT4 requires an external pullup resistor and can be pulled up to 13.2V. Discharge Pulldown Input 4. During normal operation, DISC4 is high impedance. During a fault condition or power-down, DISC4 provides an 85mA sink current. Set Monitored Threshold 3 Input. Monitor a voltage by setting the threshold with an external resistive divider. The SET3 threshold is 0.5V. Open-Drain Output 3. When the voltage at SET2* is above 0.5V, OUT3 goes high impedance. OUT3 requires an external pullup resistor and can be pulled up to 13.2V. Discharge Pulldown Input 3. During normal operation, DISC3 is high impedance. During a fault condition or power-down, DISC3 provides an 85mA sink current. Set Monitored Threshold 2 Input. Monitor a voltage by setting the threshold with an external resistive divider. The SET2 threshold is 0.5V. Open-Drain Output 2. When the voltage at SET1* is above 0.5V, OUT2 goes high impedance. OUT2 requires an external pullup resistor and can be pulled up to 13.2V. Discharge Pulldown Input 2. During normal operation, DISC2 is high impedance. During a fault condition or power-down, DISC2 provides an 85mA sink current.
4 5 6 7 8 9 10 11 12 13
4 5 6 7 8 9 10 11 12 13
EN SET4 OUT4 DISC4 SET3 OUT3 DISC3 SET2 OUT2 DISC2
14
14
Enable Hold Input. When EN_HOLD is low, the device does not start the reverseEN_HOLD sequencing process regardless of the status of the SHDN input. Reverse sequencing is allowed when this input is pulled high. Connect to ABP if unused. Open-Drain Bus Removal Output. REM goes high impedance when all DISC_ inputs are below the DISC_ power low threshold (VTH_PL). REM goes low when any DISC_ input goes above VTH_PL. REM requires an external pullup resistor and can be pulled up to 13.2V. Discharge Pulldown Input 1. During normal operation, DISC1 is high impedance. During a fault condition or power-down, DISC1 provides an 85mA sink current. Open-Drain Output 1. When the voltage at EN* is above 0.5V, OUT1 goes high impedance. OUT1 requires an external pullup resistor and can be pulled up to 13.2V.
15
15
REM
16 17
16 17
DISC1 OUT1
*This applies to the MAX16051. For the MAX16050, see Table 1 for the output sequence order.
6
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability
Pin Description (continued)
PIN MAX16050 18 MAX16051 18 NAME SET1 FUNCTION Set Monitored Threshold 1 Input. Monitor a voltage by setting the threshold with an external resistive divider. The SET1 threshold is 0.5V. Open-Drain Overvoltage Output. When any of the SET_ voltages exceed their 0.55V overvoltage threshold, OV_OUT goes low. When all of the SET_ voltages are below their overvoltage threshold, OV_OUT goes high impedance after a short propagation delay. Open-Drain Reset Output. When any of the monitored voltages (including EN) falls below its threshold, SHDN is pulled low, or FAULT is pulled low, RESET asserts and stays asserted for at least the minimum reset timeout period after all of these conditions are removed. The reset timeout is 128ms (typ) when TIMEOUT is connected to ABP or can be adjusted by connecting a capacitor from TIMEOUT to GND. FAULT Synchronization Input/Output. While EN = SHDN = high, FAULT is pulled low when any of the SET_ voltages falls below their respective threshold. Pull FAULT low manually to assert a simultaneous power-down. FAULT is internally pulled up to ABP by a 100k resistor. Active-Low Shutdown Input. When SHDN is pulled low, the device will reverse sequence for power-down operation. SHDN is internally pulled up to ABP by a 100k resistor. Adjustable Sequence Delay Timing Input. Connect a capacitor from DELAY to GND to set the sequence delay between each OUT_. Leave DELAY unconnected for a 10s (typ) delay. Adjustable Reset Timeout Input. Connect a capacitor from TIMEOUT to GND to set the reset timeout period. Connect TIMEOUT to ABP for the fixed timeout of 128ms (typ). Leave TIMEOUT unconnected for a 10s (typ) delay. Sequence Order Select Inputs. SEQ1, SEQ2, and SEQ3 allow the order of sequencing for each supply to be programmable (Table 1). Charge-Pump Output. An internal charge pump boosts CP_OUT to (VCC + 5V ) to provide a pullup voltage that can be used to drive external n-channel MOSFETs. CP_OUT sources up to 25A. Discharge Pulldown Input 5. During normal operation, DISC5 is high impedance. During a fault condition or power-down, DISC5 provides an 85mA sink current. Open-Drain Output 5. When the voltage at SET4 is above 0.5V, OUT5 goes high impedance. OUT5 requires an external pullup resistor and can be pulled up to 13.2V. External Set Monitored Threshold 5. Monitor a voltage by setting the threshold with an external resistive divider. The SET5 threshold is 0.5V. Exposed Pad. EP is internally connected to GND. Connect EP to the GND plane for improved heat dissipation. Do not use EP as the only ground connection.
MAX16050/MAX16051
19
19
OV_OUT
20
20
RESET
21
21
FAULT
22
22
SHDN
23
23
DELAY
24 25 26 27 28
24 -- -- -- 28
TIMEOUT SEQ1 SEQ2 SEQ3 CP_OUT
-- -- -- --
25 26 27 --
DISC5 OUT5 SET5 EP
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7
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
Functional Diagram
VCC
MAX16050 MAX16051
CHARGE PUMP INTERNAL VCC/UVLO ABP OUT1-OUT4 (OUT1-OUT5) CP_OUT
COMP 250mV SET1-SET4 (SET1-SET5) COMP 85mA
DISC1-DISC4 (DISC1-DISC5)
RESET
VREF CONTROL LOGIC OV_OUT
FAULT EN COMP REM EN_HOLD
SEQ1-SEQ3 (MAX16050 ONLY)
ABP
ABP
( ) ARE FOR MAX16051 ONLY.
GND
TIMEOUT
DELAY
8
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
VTH_EN EN
SHDN
tDELAY V1
VTH VTH_PL tDELAY VTH
V2 tDELAY V3 tDELAY V4 VTH VTH
tRP RESET
REM
Figure 1. Sequencing Timing Diagram with Reverse Order Power-Down Using SHDN
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9
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
VTH_EN EN
VTH_EN
SHDN tDELAY VTH V1 tDELAY V2 VTH VTH_PL
tDELAY V3
VTH
tDELAY V4
VTH
tRP RESET
REM
Figure 2. Sequencing Timing Diagram with Simultaneous Order Power-Down Using EN
10
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
tFAULT-PW FAULT
tDELAY V1
VTH_PL
V2
V3 VTH_PL
V4
RESET
REM
Figure 3. Sequencing Timing Diagram During a System Fault
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11
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
PART DOES NOT RESPOND TO EN FALLING...
EN
...UNTI
L EN_HOLD GOES HIGH
EN_HOLD CONNECTED TO REM OF THE SECOND IC
V1 V2
V3
V4
Figure 4. Power-Down Characteristics when REM of the Second IC is Connected to EN_HOLD of the First IC
12
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
Detailed Description
The MAX16050 monitors up to 5 voltages (Figure 5) with the ability to sequence up to 4 voltages, while the MAX16051 monitors up to 6 voltages with the ability to sequence up to 5 voltages. These devices control system power-up and power-down in a particular sequence order. The MAX16050/MAX16051 turn off all supplies and assert a reset to the processor when any of the voltages falls below its respective threshold. The MAX16050/MAX16051 offer an 85mA pulldown feature that helps discharge the output capacitance of DC-DC converters to ensure timely power-down. In addition, the MAX16050/MAX16051 also reverse sequence, monitoring each power-supply output voltage present at the associated DISC_ input and ensuring that the voltage falls below 250mV before turning off the next supply. The MAX16050 provides three sequence logic inputs, which select the sequence order from 24 possible
VBUS DC-DC EN DC-DC EN DC-DC EN DC-DC EN V1 V2 V3 V4
combinations (Table 1). In the default mode (SEQ1 = SEQ2 = SEQ3 = High Impedance), the power-up sequence is OUT1OUT2OUT3OUT4. The MAX16051 features an additional channel and the sequence order is fixed at OUT1OUT2OUT3 OUT4OUT5. For complex systems with a large number of power supplies, the MAX16050/MAX16051 can be used in a daisy-chain configuration. Reverse sequencing in the daisy-chained configuration is still possible. The MAX16050/MAX16051 keep all OUT_ low (all of the supplies in the off-state) until four conditions are met. 1) The voltage at ABP exceeds the undervoltage lockout threshold. 2) The voltage at the analog enable input (EN) is above its threshold. 3) The shutdown input, SHDN, is not asserted. 4) All DISC_ voltages must be below 250mV.
VPU
SET1
DISC1
OUT2
SET2
DISC2
OUT3
SET3
DISC3
OUT4
SET4
VCC RESET OV_OUT
EN
MAX16050
GND EN_HOLD SEQ1 SEQ2 SEQ3 SHDN DELAY ON OFF TIMEOUT CP_OUT ABP
DISC4 FAULT REM
Figure 5. Typical Connection for Sequencing Four DC-DC Converters
______________________________________________________________________________________ 13
OUT1
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
When all of these conditions are met, the device starts the power-sequencing process by turning on OUT1-OUT_ in the sequence order. The sequence delay between each OUT_ is the time required for the power-supply voltage to exceed the undervoltage threshold plus the additional time delay set by the external delay capacitor; if no capacitor is connected to the sequence delay timing input (DELAY), only a short propagation delay (10s) occurs. As each voltage meets its respective threshold, the next OUT_ in the sequence goes high impedance (open-drain output), allowing the next power supply to turn on, which is then monitored by the next input stage. When all of the voltages exceed their respective thresholds, the reset output (RESET) deasserts after a reset timeout period to allow the system controller to start operating. After sequencing is complete, if any SET_ input drops below its threshold, a fault is detected. All power supplies are simultaneously turned off by the OUT_ outputs asserting low, the RESET output asserting, the DISC_ current pulldown turning on, and the FAULT output pulling low for at least 1.9s. The MAX16050/MAX16051 will then be ready to power on again. Sequencing begins as soon as the four startup conditions are met.
Sequencing
The MAX16050 features three three-state sequence logic inputs that select one of the 24 possible sequence orders (Table 1). These inputs allow the sequence order to be changed even after the board layout is finalized. The MAX16051 offers five channels and the device powers up in a fixed order from OUT1 to OUT5.
Table 1. MAX16050 Sequencing Table Logic
SEQ1 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Low Low Low Low Low Low Low Low Low High High High High High High SEQ2 High-Z High-Z High-Z Low Low Low High High High High-Z High-Z High-Z Low Low Low High High High High-Z High-Z High-Z Low Low Low SEQ3 High-Z Low High High-Z Low High High-Z Low High High-Z Low High High-Z Low High High-Z Low High High-Z Low High High-Z Low High SEQUENCE ORDER FIRST SUPPLY OUT1 OUT1 OUT1 OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT3 OUT3 OUT3 OUT3 OUT3 OUT3 OUT4 OUT4 OUT4 OUT4 OUT4 OUT4 SECOND SUPPLY OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 OUT1 OUT1 OUT3 OUT3 OUT4 OUT4 OUT1 OUT1 OUT2 OUT2 OUT4 OUT4 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 THIRD SUPPY OUT3 OUT4 OUT2 OUT4 OUT2 OUT3 OUT3 OUT4 OUT1 OUT4 OUT1 OUT3 OUT2 OUT4 OUT1 OUT4 OUT1 OUT2 OUT2 OUT3 OUT1 OUT3 OUT1 OUT2 FOURTH SUPPLY OUT4 OUT3 OUT4 OUT2 OUT3 OUT2 OUT4 OUT3 OUT4 OUT1 OUT3 OUT1 OUT4 OUT2 OUT4 OUT1 OUT2 OUT1 OUT3 OUT2 OUT3 OUT1 OUT2 OUT1
14
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability
Charge-Pump Output (CP_OUT)
The MAX16050/MAX16051 feature an on-chip charge pump that drives its output voltage to 5V above VCC, and it can be used as a pullup voltage to drive one or more external n-channel MOSFETs (see the Typical Operating Circuit). The charge-pump output can be modeled as a 25A current source with a compliance voltage of (VCC + 5V); the slew rate can be controlled by connecting a capacitor from the gate of the MOSFET to ground. When using CP_OUT to provide the pullup voltage for multiple MOSFETs, ensure that the voltage is enough to enhance a MOSFET despite the load of the other pullup resistors (which may be connected to outputs that are deasserted low). after all of these conditions are removed. Connect a capacitor from TIMEOUT to GND to adjust the reset timeout period. Connect TIMEOUT to ABP for the fixed timeout of 128ms (typ). Leave TIMEOUT unconnected for a 10s (typ) timeout period.
MAX16050/MAX16051
FAULT Input/Output
The FAULT input/output asserts to signal a fault if any of the SET_ monitored voltages falls below its threshold while EN = SHDN = high. FAULT is internally pulled up to ABP by a 100k resistor. FAULT also can be used as an input. Pull FAULT low to simultaneously shut down the OUT_ outputs . For multichip solutions, all of the FAULT input/outputs can be connected together. In case of a fault condition, all outputs on every device are turned off and the internal pulldown circuitry is activated simultaneously.
Disabling Channels
If any channel is not used, connect the associated SET_ input to another SET_ input that is previous to the disabled channel in the sequence order. Connect DISC_ of the disabled channel to GND or leave it unconnected. The channel exclusion feature adds more flexibility to the device in a variety of different applications.
Overvoltage Fault Output (OV_OUT)
The MAX16050/MAX16051 include an overvoltage fault output. OV_OUT is an open-drain output and requires an external pullup resistor. When any of the SET_ voltages exceed their 0.55V overvoltage threshold, OV_OUT goes low. When all of the SET_ voltages are below their overvoltage threshold, OV_OUT goes high impedance after a short propagation delay.
SHDN and EN Inputs
The shutdown input (SHDN) initiates a reverse sequencing event. When SHDN is brought low, the device will sequentially power down in reverse order. During this period, all DISC_ inputs are monitored to make sure the voltage of each supply falls below 250mV before allowing the next supply to shut down. The next OUT_ goes low as soon as the previous DISC_ input drops below 250mV without any capacitor-adjusted delay. This continues until all supplies are turned off. SHDN is internally pulled up to ABP. When EN falls below its threshold, the device performs a simultaneous power-down and does not reverse sequence. When either SHDN or EN initializes the power-down event, the reset output (RESET) immediately asserts. At the end of the power-down event, when all DISC_ voltages are below 250mV, the bus removal output (REM) goes high impedance.
Discharge Inputs (DISC_)
The discharge inputs (DISC_) discharge power-supply capacitors during a power-down or fault event and monitor power-supply output voltages during reverse sequencing. When an OUT_ output goes low, the associated DISC_ activates an 85mA pulldown current to discharge any output capacitors. This helps the power-supply output drop below the 250mV level so the next power supply can be turned off. During normal operation, DISC_ is high impedance and will not load the circuit.
Bus Removal Output (REM)
The MAX16050/MAX16051 include an open-drain bus removal output (REM) that indicates when it is safe to disconnect the input power after a controlled powerdown operation. REM monitors DISC_ voltages and goes low when any DISC_ input voltage goes above the DISC_ power low threshold (VTH_PL). REM goes high when all DISC_ inputs are below the DISC_ power low threshold (VTH_PL). For a visual signal of when it is unsafe to remove a powered board from the bus, connect an LED to REM.
Reset Output (RESET)
The MAX16050/MAX16051 include a reset output. RESET is an open-drain output and requires an external pullup resistor. When any of the monitored voltages falls below its threshold, SHDN is pulled low, EN falls below its threshold, or FAULT is pulled low, RESET asserts and stays asserted for at least the minimum reset timeout period
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15
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
Enable Hold Input (EN_HOLD)
When EN_HOLD is low, a high-to-low transition on SHDN or on EN is ignored. EN_HOLD must be high for SHDN or EN to disable the device. This feature is used when multiple MAX16050/MAX16051s are daisychained (see Figure 7). Connect EN_HOLD to ABP if not used. equation to estimate the value of the resistors based on the amount of acceptable error: e x V1TH R1 = A ISET where eA is the fraction of the maximum acceptable absolute resistive divider error attributable to the input leakage current (use 0.01 for 1%), V1TH is the powergood threshold for the power supply being monitored, and ISET is the worst-case SET_ input leakage current (see the Electrical Characteristics table). Calculate R2 as follows: R2 = VTH x R1 V1TH - VTH
Delay Time Input (DELAY)
Connect a capacitor (CDELAY) between DELAY and GND to adjust the sequencing delay period (tDELAY) that occurs between sequenced channels. Use the following formula to estimate the delay: tDELAY = 10s + (500k x CDELAY) where tDELAY is in seconds and CDELAY is in Farads. Leave DELAY unconnected for the default 10s (typ) delay.
Reset Timeout Input (TIMEOUT)
Connect a capacitor (C TIMEOUT ) from TIMEOUT to GND to set the reset timeout period. After all SET_ inputs exceed their thresholds (VTH), RESET remains low for the programmed timeout period, tRP, before deasserting (see Figure 1). Use the following formula to estimate the reset timeout period: tRP = 10s + (500k x CTIMEOUT) where tRP is in seconds and CTIMEOUT is in Farads. Leave TIMEOUT unconnected for the default 10s (typ) timeout delay or connect TIMEOUT to ABP to enable a fixed 128ms (typ) timeout.
Pullup Resistor Values
The exact value of the pullup resistors for the opendrain outputs is not critical, but some consideration should be made to ensure the proper logic levels when the device is sinking current. For example, if VCC = 3.3V and the pullup voltage is 5V, keep the sink current less than 3.2mA as shown in the Electrical Characteristics table. As a result, the pullup resistor should be greater than 1.6k. For a 13.2V pullup, the resistor should be larger than 4.1k. Extra care must be taken when using CP_OUT as the pullup voltage. If multiple pullup resistors are connected to CP_OUT and one or more of the connected OUT_ outputs are asserted, the current drawn can drop the CP_OUT voltage enough to prevent an enabled MOSFET from turning on completely.
V1TH VBUS
Applications Information
Resistor Value Selection
The MAX16050/MAX16051 feature four and five SET_ inputs, respectively, and the threshold voltage (VTH) at each SET_ input is 0.5V (typ). To monitor a voltage V1TH, connect a resistive divider network to the circuit as shown in Figure 6, and use the following equation to calculate the monitored threshold voltage: R1 V1TH = VTH x 1 + R2 Balance accuracy and power dissipation when choosing the external resistors. The input to the voltage monitor is a high-impedance input with a small 100nA leakage current. This leakage current contributes to the overall error of the threshold voltage, and this error is proportional to the value of the resistors used to set the threshold. Small-valued resistors reduce the error but increase the power consumption. Use the following
16
R1 SET_
VCC RESET
R2
MAX16050 MAX16051
GND
Figure 6. Setting the SET_ Input
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability
Daisy-Chaining the MAX16050/MAX16051
The MAX16050/MAX16051 can be daisy-chained to sequence and monitor a large number of voltages (Figure 7). When a fault occurs on any of the monitored inputs, FAULT goes low, signaling a fast power-down. Connect all FAULT pins of the MAX16050/MAX16051 together to ensure that all power supplies are turned off during a fault. In Figure 7, SHDN is pulled low to initiate the powerdown sequence. When all of the supply voltages monitored by U2 are off, the bus removal output (REM) goes high, thereby allowing U1 to start sequencing down. REM normally is at a logic-low state when all voltages are good. Connect U2's REM to U1's EN_HOLD to force U1 to stay on even if EN and SHDN are pulled low. This enable-and-hold circuitry allows the system to power down correctly.
MOSFET Selection
The external pass MOSFET connects in series with the sequenced power-supply source. Since the load current and the MOSFET drain-to-source impedance (RDSON) determine the voltage drop, the on-characteristics of the MOSFET affect the load supply accuracy. For highest supply accuracy and lowest voltage drop, select a MOSFET with an appropriate drain-to-source on-resistance with a gate-to-source bias of 4.5V to 6.0V (see Table 2).
MAX16050/MAX16051
Layout and Bypassing
For better noise immunity, bypass VCC to GND with a 0.1F capacitor installed as close to the device as possible. Bypass ABP to GND with a 1F capacitor installed as close to the device as possible; ABP is an internally generated voltage and must not be used to supply more than 1mA to external circuitry. Connect the exposed pad (EP) to the ground plane for improved heat dissipation. Do not use EP as the only ground connection for the device.
Table 2. Recommended MOSFETs
MANUFACTURER PART FDC633N FDP8030L FDB8030L FDD6672A FDS8876 Si7136DP Si4872DY Vishay SUD50N02-09P Si1488DH VDS (V) 30 30 30 30 20 30 20 20 VGSth (V) 0.67 1.5 1.2 2.5 (max) 3 1 3 0.95 RDSON AT VGS = 4.5V (m) 42 4.5 9.5 17 4.5 10 17 49 IMAX AT 50mV VOLTAGE DROP (A) 1.19 11.11 5.26 2.94 11.11 5 2.94 1.02 Qg (nC) (TYP) 11 120 33 15 24.5 27 10.5 6 FOOTPRINT Super SOTTM-6 TO-220 TO-263AB TO-252 SO-8 SO-8 SO-8 TO-252 SOT-363 SC70-6 TO220AB D2PAK TO-262 TO-220AB TO220AB D2PAK TO-262 SOT23-3 Micro3TM
Fairchild
IRL3716 IRL3402 International Rectifier IRL3715Z
20 20 20
3 0.7 2.1
4.8 10 15.5
10.4 5 3.22
53 78 (max) 7
IRLML2502
20
1.2
45
1.11
8
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17
Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
VBUS VBUS
DC-DC EN DC-DC EN DC-DC EN DC-DC EN
V1 V2 V3 V4
DC-DC EN DC-DC EN DC-DC EN DC-DC EN
V5 V6 V7 V8
DISC1
DISC2
DISC3
DISC4
SET1
OUT1
OUT2
SET2
OUT3
SET3
OUT4
SET4
DISC1
DISC2
DISC3
DISC4
SET1
OUT1
OUT2
SET2
OUT3
SET3
OUT4
SET4
VPU
VCC
CP_OUT
VCC
CP_OUT
EN
U1 MAX16050
RESET
EN
U2 MAX16050
RESET
GND
OV_OUT
GND
OV_OUT
TIMEOUT
TIMEOUT
ABP SHDN SEQ1 SEQ2 SEQ3 REM
FAULT DELAY
ABP SHDN SEQ1 SEQ2 SEQ3 REM
FAULT DELAY
EN_HOLD
EN_HOLD
PULL SHDN LOW TO INITIATE A REVERSE ORDER SHUTDOWN OF ALL 8 SUPPLIES
Figure 7. Daisy-Chaining Two Devices to Sequence Up to 8 Voltages
18
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability
Typical Operating Circuit
VBUS V4 DC-DC EN DC-DC EN DC-DC EN V1 V2 V3
MAX16050/MAX16051
SET1
DISC1
SET2
DISC2
SET3
DISC3
SET4
DISC4
OUT2
OUT3
OUT1
OUT4
VPU CP_OUT
VCC
EN
RESET
MAX16050
OV_OUT GND FAULT EN_HOLD ON SEQ1 SEQ2 SEQ3 OFF SHDN TIMEOUT
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DELAY
REM
ABP
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
Pin Configurations (continued)
PROCESS: BiCMOS
FAULT RESET DISC1 OUT1 SET1 REM
Chip Information
TOP VIEW
21 SHDN 22 DELAY 23 TIMEOUT 24 DISC5 25 OUT5 26 SET5 27 CP_OUT 28 1 VCC
20
19
OV_OUT
18
17
16
15 14 13 12 EN_HOLD DISC2 OUT2 SET2 DISC3 OUT3 SET3
MAX16051
*EP
11 10
+
2 GND 3 ABP 4 EN 5 SET4
9 8
6 OUT4
7 DISC4
THIN QFN (4mm x 4mm)
*EP = EXPOSED PAD
20
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS
MAX16050/MAX16051
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Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability MAX16050/MAX16051
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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